There have conventionally and widely been used semiconductor apparatuses in which both a low potential reference circuit and a high potential reference circuit are incorporated for power apparatuses and the like. A semiconductor apparatus of this kind is generally structured such as shown in FIG. 16. That is, the semiconductor apparatus has a low potential reference circuit region 1 and a high potential reference circuit region 2, and the high potential reference circuit region 2 is surrounded by a high withstand voltage separating region 3 formed with resurf structure or the like. Furthermore, there are arranged high withstand voltage NMOS 5 and high withstand voltage PMOS 6 for signal transmission (level shift) between the low potential reference circuit region 1 and the high potential reference circuit region 2. To be specific, the high withstand voltage NMOS 5 arranged in the low potential reference circuit region 1 is used for level shift from the low potential reference circuit region 1 to the high potential reference circuit region 2. On the other hand, for level shift from the high potential reference circuit region 2 to low potential reference circuit region 1, the high withstand voltage PMOS 6 arranged in the high potential reference circuit region 2 is used. Drain wirings of the high withstand voltage NMOS 5 and the high withstand voltage PMOS 6 are drawn out to a region of output side from its input side crossing over the high withstand voltage separating region 3.
FIG. 17 shows an example of a circuit which conducts level shift from the low potential reference circuit region 1 to the high potential reference circuit region 2. This circuit has a high withstand NMOS 5, a pull-up resistor 101, and a Zener diode 102. Along ON/OFF of the high withstand voltage NMOS 5, there is caused a potential difference at the drain which corresponds to power voltage in a high potential reference circuit region 2. Thereby, level shift is conducted between the low potential reference circuit region 1 and the high potential reference circuit region 2. For example, suppose that power voltages of both the low potential reference circuit region 1 and the high potential reference circuit region 2 are 15V and potential difference between the low potential reference circuit region 1 and the high potential reference circuit region 2 is 1000V. In this case, a signal voltage of which is swung between 0V and 15V in the low potential reference circuit region 1 is converted to a signal swinging between 1000V and 1015V through the circuit of FIG. 17. Thereby, a signal transmitted from the low potential reference circuit region 1 is usable within the high potential reference circuit region 2.
In a semiconductor apparatus which thus conducts level shift between the low potential reference circuit regional and the high potential reference circuit region 2, a signal is transmitted through metal wirings (drain wirings) formed on its surface. Drain wirings cross over the low potential reference circuit region 1, high withstand voltage separating region 3 and the like, and there is an interlayer dielectric in between. In this case, potential difference between drain wirings (high potential) and the surface of the semiconductor device (low potential) is large. As a result, withstand-ability against voltage lowers due to drain wirings. Usually, interlayer dielectric between drain wirings and the surface of the semiconductor device is formed thick for resolving the above-mentioned problem. However, in case of a semiconductor apparatus of which potential difference between a high potential reference circuit region and a low potential reference circuit region exceeds 600V, it leads complication of wiring process due to thickened interlayer dielectric, cost-up, and the like.
As technology to resolve the above-mentioned problem, Patent Document 1, for example, discloses a semiconductor apparatus in which a high withstand voltage separating region and drift layer of a high withstand MOS for level shift are formed as a package and a drain is formed in a circuit region at output side. In this document, it is stated that level shift can be done without causing a problem regarding withstand-ability of voltage, since drain wirings are wired without crossing over a high withstand voltage separating region or a low potential reference circuit region.
Furthermore, in addition to the above, Patent Document 2, for example, discloses a semiconductor apparatus in which a portion of an N type high withstand voltage separating region is partitioned with a P type slit region and a high withstand voltage NMOS for level shift is formed at the partitioned portion. That is, N type drain region of a high withstand voltage NMOS and N type layer within a high potential reference circuit region are made to face each other sandwiching a P type slit region. Furthermore, drain wirings of high potential are arranged above the slit region. In this semiconductor apparatus, the slit region is pinched off (depletion regions formed with both of N type layers are incorporated into one). By pinching off the slit. region, a surface of the P type slit region has potential almost same as N type layers at its both sides. It is stated that influence of drain wirings is restrained thereby.
Furthermore, in addition to the above, Patent Document 3, for example, discloses a semiconductor apparatus of SOI structure. This semiconductor apparatus is provided with an insulating region which extends from the main surface of semiconductor apparatus to the buried insulating layer and with a drain wiring above the insulating region. It is stated that influence of drain wirings is restrained because intervals of drain wirings (high potential) and semiconductor layer can be made large.
[Patent Document 1] JP Laid-Open Patent Publication No. 9-55498
[Patent Document 2] JP Laid-Open Patent Publication No. 9-283716
[Patent Document 3] JP Patent Publication No. 3201719
The above-referenced documents disclose inventions to prevent potential difference between drain wirings and a surface of a semiconductor device from being large when level shift is done. However, semiconductor apparatuses in the above-reference documents have had following problems.
That is, regarding the semiconductor apparatus of Patent Document 1, in case high withstand voltage MOS is an NMOS, N drain layer of the NMOS is formed in contact with N type layer of the high potential reference circuit region. Therefore, the N drain layer of the high withstand voltage NMOS and N type layer of the high potential reference circuit region are electrically connected to each other. Therefore, there is required a system to enlarge parasitic resistance between the N drain layer of the high withstand voltage NMOS and the N type layer in the high potential reference circuit region. For that reason, in the semiconductor apparatus of the Patent Document 1, the high withstand voltage separating region is bent toward the low potential reference circuit region to form the high withstand voltage NMOS on the bent portion. That is, parasitic resistance is made large by making a distance between the N drain layer of the high withstand voltage NMOS and the N type layer in the high potential reference circuit region long. However, bending the high withstand voltage separating region leads to increase of chip area, which is obstacle to miniaturization of a substrate, as entirety. Furthermore, since it is impossible to completely insulate the N drain layer of the high withstand NMOS and the N type layer in the high potential reference circuit region, leak current is inevitable. Therefore, excessive power consumption occurs.
Furthermore, in the semiconductor apparatus of Patent Document 2, positioning of N drain layer of the high withstand voltage NMOS and N type layer in the high potential reference circuit region is intended to generate depletion layer between those N type layers. However, in case distance between the two N type layers is too short, punch-through breakdown occurs between N drain layer of the high withstand voltage NMOS and N type layer in the high potential reference circuit region. That is, distance between the two N type layers must be determined taking trade-off relation of voltage withstand-ability and punch-through breakdown into consideration. Therefore, the trade-off relation is not always satisfied depending on required specification voltage and specification voltage restricts the trade-off balance.
Furthermore, as to a semiconductor apparatus disclosed in Patent Document 3, thickness of an insulating region formed below drain wiring must be made thick. Patent Document 3 describes that the insulating region is formed by means of LOCOS method (localized oxidation of silicon method). However, thickness of oxidation film feasible with LOCOS method is of about 1 to 2 μm. Accordingly, the LOCOS method is not applicable to high withstand voltage type devices. Furthermore, other than LOCOS method, there can be conceived of another method that a trench is formed at semiconductor layer and oxide film or poly crystal silicon layer is embedded inside the trench. However, with this method, thickening the insulating region is not sufficient for enhancing voltage withstand-ability between drain wiring and the semiconductor layer, and width of the insulating layer must be taken wide to some extent. In this connection, in case a wide trench exceeding 2 μm is formed, it is difficult to fill the trench with oxide film or poly crystal silicon film inside, which lacks feasibility. Furthermore, in the semiconductor apparatus of Patent Document 3, the semiconductor layer constituting devices is separated by the insulating region. Therefore, potential distribution gets uneven at the border portion of the semiconductor region and the insulating region and electric field is likely to concentrate at the border.
The present invention has been made to resolve problems the above mentioned conventional semiconductor apparatuses have had. That is, the present invention intends to provide a semiconductor apparatus incorporating both low potential reference circuits and high potential reference circuits, capable of conducting level shift between the low potential reference circuits and high potential reference circuits and excellent in compact design and voltage withstand-ability.